As is known in the art, historically, the focus in the design of digital-to-analog converters (DACs) has been on simultaneously achieving the highest possible bandwidth and dynamic range. Obtaining high output power has been limited due to the use of relatively low-voltage based, technologies (Si and SiGe bipolar, Si CMOS, InP HBT) and the architectures that emphasized the bandwidth and dynamic range. Additionally, a high-quality DAC output signal could be amplified by an amplifier to reach the required output power levels. However, use of an amplifier at the DAC output comes at the cost of dynamic range—efficiency trade-off. To preserve the dynamic range, an amplifier must be operated in a linear range with relatively low efficiency, resulting in the high prime power consumption and, often, thermal management complications. Using amplifier in the nonlinear regime with higher efficiency and alleviated thermal issues compromises amplifier linearity and, as a result, the dynamic range of the output signal.
In a traditional digital-analog converter (DAC) design, the emphasis is placed on simultaneously maximizing bandwidth and dynamic range while minimizing power consumption with the output power being only a 2nd order requirement, As a result, state-of art DACs (and direct digital synthesizers (DDSs)) exhibit relatively low output power levels (<0 dBm).
For systems that require higher output power levels (for example, Active Electronically Scanned Arrays (AESAs)) with element-level digital beamforming architecture), the DAC output needs to be amplified by either: Linear amplifiers to preserve the dynamic range at the expense of efficiency; or Non-linear amplifiers to maximize efficiency at the expense of dynamic range
Therefore, there is a need for a DAC having a power-efficiency with both high bandwidth, high dynamic range and high output power.